The invention relates to semiconductor devices and circuits, and, more particularly, to semiconductor memories with error correction.
Dynamic random access memories (DRAMs) typically store a bit as electric charge in a capacitor and access the capacitor through a field effect transistor. This exposes such a memory cell to soft errors from charge generated by subatomic particles penetrating the capacitor-side junction of the access transistor.
Various approaches to soft error correction have been attempted. For example, Furutani et al, A Built-In Hamming Code ECC Circuit for DRAM's, 24 IEEE JSSC 50 (1989) and Kalter et al, A 50-ns 16-Mb DRAM with a 10-ns Data Rate and On-Chip ECC, 25 IEEE JSSC 1118 (1990) describe DRAMs with additional error correction circuitry for error correction upon read operations and refresh operations (which is a read followed by a write back). This error correction compensates for soft errors but slows down the access time of the DRAM due to the error correction circuitry delay.